The present invention relates generally to pitch size in integrated circuits (ICs). More particularly, the present invention relates to a process for fabricating reduced pitch size in integrated circuits.
The semiconductor or integrated circuit (IC) industry aims to manufacture integrated circuits (ICs) with higher and higher densities of devices on a smaller chip area to achieve greater functionality and to reduce manufacturing costs. This desire for large scale integration has led to continued shrinking of circuit dimensions and device features. The ability to reduce the size of structures, such as, gate lengths in field-effect transistors and the width of conductive lines, is driven by lithographic performance.
Feature size has been steadily decreasing with the help of shorter lithographic or exposure wavelengths and resolution enhancement techniques, such as, phase shifting marks and off-axis illumination. In contrast, the distance between adjacent feature/space combinations, i.e., the pitch, has proven more difficult to reduce. Even using shorter lithographic wavelengths and various resolution enhancement techniques, the pitch is usually constrained, at best, to a dimension approximately equal to the lithographic wavelength.
Presently, with 193 nanometer (nm) lithographic systems, the minimum achievable pitch is approximately 300 nm. And with shorter lithographic wavelengths (e.g., 157, 126, or 13.4 nm), proximity effect further constrains fabrication of smaller pitches in ICs.
Thus, there is a need for a method and apparatus of fabricating an integrated circuit having a pitch smaller than the lithographic wavelength associated therewith. There is a further need for a method of and apparatus for fabricating an integrated circuit having a reduced pitch that utilize existing equipment and materials and do not significantly decrease throughout.
An exemplary embodiment relates to a method of fabricating reduced pitch in an integrated circuit. The integrated circuit includes a patterned photoresist layer. The patterned photoresist layer is patterned in accordance with a pattern on a mask or reticle and exposed to a first radiation at a lithographic wavelength. The method includes providing a second radiation to at least one area of the patterned photoresist layer. The patterned photoresist layer includes a developed exposed area, the developed exposed area including sidewalls and a bottom. The method further includes transforming the sidewalls of the developed exposed area to change the width of the developed exposed area in response to the second radiation. The method still further includes positioning the pattern on the mask or reticle relative to the patterned photoresist layer so that the pattern on the mask or reticle is not aligned with the patterned photoresist layer.
Another exemplary embodiment relates to an integrated circuit fabrication process. The process includes changing a first aperture formed on a photoresist layer provided over a semiconductor substrate. The process further includes forming a second aperture on the photoresist layer in accordance with a mask or reticle used to form the first aperture. The mask or reticle is not in alignment with the first aperture formed on the photoresist layer. The first aperture defines a first feature in the substrate and the second aperture defines a second feature in the substrate.
Still another exemplary embodiment relates to an integrated circuit fabrication process. The process includes (a) reducing a width associated with a current patterned area in a photoresist layer provided over a substrate. The process further includes (b) patterning the substrate in accordance with the reduced width current patterned area in the photoresist layer, to form a current set of features in the substrate. The process still further includes (c) transferring a pattern on a mask or reticle onto the photoresist layer to form the next current set of features in the substrate, and (d) repeating steps (a)-(c) a plurality of times, as desired. All of the sets of features are similar to each other. A density of the features formed on the substrate is greater than a density of the features provided as the pattern on the mask or reticle. The reducing step (a) includes melting and flowing sidewalls of the current patterned area.